FIGS. 1(a)-(h) illustrate fabrication steps in a conventional process for making an electrically erasable, programmable read-only memory (EEPROM) cell. As shown in FIG. 1(a), an oxide film 13 and a nitride film 15 are respectively deposited on a p-type semiconductor substrate 11. A portion of the surface of substrate 11 corresponding to a source region of the ZEPROM cell is then exposed by etching oxide film 13 and nitride film 15.
As shown in FIG. 1(b), an n+-type source region 17 is formed by ion implanting n-type impurities into substrate 11 using oxide film 13 and nitride film 15 as a mask. The substrate is then subjected to a conventional field oxidation process to form a first field oxide film 19. Nitride film 15 and oxide film 13 are then sequentially removed.
As shown in FIG. 1(c), oxide film 21 and nitride film 23 are then respectively deposited on semiconductor substrate 11. These layers are then etched to expose a portion of the substrate surface corresponding to a drain region of the EEPROM cell.
As shown in FIG. 1(d), n+-type drain region 25 is formed by ion implanting N-type impurities into the exposed substrate surface illustrated in FIG. 1(c), using oxide film 21 and nitride film 23 as an implantation mask. The substrate is again subjected to a conventional field oxidation process to form a second field oxide film 27. As further shown in FIG. 1(d), the N+-type drain region 25 and second field oxide film 27 are spaced a predetermined distance in the substrate surface from N+ source region 17 and first field oxide film 19, which were previously formed in the steps illustrated in FIGS. 1(a)-(b). Remaining portions of oxide film 21 and nitride film 23 are then removed.
As shown in FIG. 1(e), a gate oxide film 29 is formed over an exposed portion of the substrate surface not covered by field oxide films 19 and 27. FIG. 1(f) illustrates the step of forming a tunnelling oxide film 31 over a portion of N+ drain region 25 by removing a corresponding portion of field oxide film 27 overlying drain region 25. Tunnelling oxide film 31 is formed by thinning the second field oxide film 27 over a central portion of drain region 25 by a predetermined amount so that only a thin portion of field oxide film 27 remains.
As shown in FIG. 1(g), a first floating gate electrode 33 of the EEPROM cell is formed by depositing a polysilicon film over the entire substrate surface including first and second oxide films 19 and 27, respectively, and the tunnelling oxide film. The polysilicon film is then patterned in a conventional manner to form floating gate electrode 33. Lastly, as shown in FIG. 1(h), a dielectric film 35 is formed on an exposed surface of floating gate 33, and a second polysilicon control gate electrode 37 of the EEPROM cell is provided on dielectric film 35. FIG. 1(h) illustrates the resulting conventional EEPROM cell.
Writing and erasing operations of the above-described conventional EEPROM cell will now be discussed with reference to FIG. 2. First, when writing or programming the EEPROM cell, a high voltage is applied to control gate 37 through a voltage application terminal V.sub.CG, and a low voltage or ground is applied to drain region 25 via a voltage application terminal V.sub.D. In this case, either a low source voltage is applied to terminal V.sub.S of the source region 17, or the source voltage is floating. As a result, electron-hole pairs are formed in the channel region between source and drain regions 17 and 25, respectively. Some of the electrons from these electron hole pairs are then injected into drain region 25 due to the large potential difference between the control gate 37 and drain region 25. These electrons then tunnel into floating gate 33 through the thin tunnelling oxide film 31. As increasing numbers of electrons accumulate in floating gate 33, the threshold voltage V.sub.T of the EEPROM cell correspondingly increases. When information is erased from the EEPROM cell, however, a low voltage or ground is applied to control gate 37 through the associated voltage application terminal V.sub.CG. Further during the erasing operation, a high voltage is applied to drain region 25 through the voltage application terminal V.sub.D, while source region voltage application terminal V.sub.S remains floating. As a result, a potential difference is created between the control gate 37 and drain region 25 which causes electrons previously accumulated on floating gate 33 to drain off to drain region 25 through tunnelling oxide film 31. As shown in FIG. 3, as increasing numbers of electrons are drained off floating gate 33 to drain region 25, the potential across tunnelling oxide 31 correspondingly decreases.
The above-described EEPROM cell, however, suffers from the following problem. Due to the high voltages involved during the erasing process, a depletion region 39 is formed between tunnelling oxide film 31 and a channel region, which includes a portion of drain region 25 beneath second oxide film 27. Specifically, a high voltage present on control gate 37 depletes a portion of the drain region where the second field oxide film 27 is thin. As a result, holes in the drain region beneath tunnelling oxide film 31 flow from drain 25 to substrate 11 as a leakage current.
Moreover, the fabrication process used to make the above described EEPROM cell is complicated. In particular, two field oxidation processes are required to form the thick field oxide films, and an etching process is also needed to etch the field oxide film to a specified thickness in order form the thin tunnelling oxide film.